 // **************************************************************
//COPYRITE (c) 2010,ISN State Key Library
//All rights reserved
//                              
//IP LIB INDEX : 
//IP Name      : 
//File Name    :counter_emac_top.v
//Module Name  :COUNTER_EMAC_TOP
//Full Name    :
//Author       :zhaoweiwei 
//Email        :zhaoquanhong123@163.com                       
//Data         :
//Version      :V1.0
//Abstract     :this module is  top module of counter module at  emac receive port
//Called by    :
//Modification history:010.12.1 zww \ufffd\u04fd\ufffd\ufffd\u0575\ufffd\ufffd\u023d\ufffd\ufffd\ufffdout_port_num\ufffd\u017a\ufffd
//**********************************************                                

//**********************
//  DEFINE MODULE PORT//
//**********************

/*
\u4f3c\u4e4e\u6df1\u5c42\u6b21\u7684\u7406\u89e3\u9700\u8981\u5bf9\u201creceive_schedule\u201d\u548c\u201cfp_class\u201d\u6709\u76f8\u5f53\u7684\u4e86\u89e3\uff0c\u4f46\u662f\u5f88\u590d\u6742
*/

/*
\u95ee\u9898\uff1a
1.\u6d41\u63a7\u5e94\u8be5\u4e0d\u4f1a\u52a0\u5728\u8f6c\u53d1\u8868\u7684\u8def\u5f84\u4e0a\uff0c\u800c\u662f\u63a5\u6536\u8c03\u5ea6\u6a21\u5757\u62ff\u5230\u4e4b\u540e\u628a\u76ee\u7684\u7aef\u53e3\u548c\u5e27\u4fe1\u606f\u4e00\u8d77\u4ea4\u7ed9\u6d41\u63a7\u2014\u2014\u2014\u2014\u56e0\u4e3a\u4ee3\u7801\u5206\u6790\u662f\uff1a\u81f3\u5c11\u7aef\u53e3\u4fe1\u606f\u4e0d\u80fd\u5728\u5e27\u957f\u4fe1\u606f\u4e4b\u540e\u7ed9\u5230\u3010\u5177\u4f53\u9700\u8981\u770b\u63a5\u6536\u8c03\u5ea6\u7684\u5904\u7406\u3011
2.flow_ctrl\u6709\u4e24\u4e2a\u6d41\u63a7\uff0c\u4e00\u4e2a\u662f\u8f6c\u53d1\u8868\u53e6\u4e00\u4e2a\u662f\u6d41\u5206\u7c7b\uff0c\u4f46\u662f\u5b83\u4eec\u53ea\u8f93\u51fa\u4e00\u4e2aresult\u7ed3\u679c\uff0c\u4e5f\u5c31\u662f\u8bf4\u4f1a\u76f8\u4e92\u5f71\u54cd\u3010\u56e0\u6b64\uff0c\u5b83\u63a7\u7684\u662f\u54ea\u91cc\u7684\u6d41\u91cf\uff1f\u3011
3.\uff08\u6216\u8bb8\uff09addr\u5c31\u662f\u67e5\u8868\u5f97\u5230\u7684\u7aef\u53e3\u3010\u770b\u63a5\u6536\u8c03\u5ea6\u7684\u5904\u7406\u3011
4.CPU\u7ed9\u5230\u7684\u4e5f\u662f\u4e00\u4e2a\u7edd\u5bf9\u4fe1\u606f\uff0c\u56e0\u6b64CPU\u6216\u8005\u63a5\u53e3\u5904\u81f3\u5c11\u9700\u8981\u505a\u4e00\u4e2a\u201c\u9884\u5904\u7406\u201d\u3010\u8fd9\u4e2a\u548c\u8f6c\u53d1\u8868\u7684\u60c5\u51b5\u662f\u4e00\u6837\u7684\u3011
5.\u4ee4\u724c\u8bbe\u7f6e\u7684\u662f\uff1a\u5982\u679c\u5f53\u524d\u4ee4\u724c\u6570\u4e0d\u80fd\u8fc7\u4e00\u4e2a\u6700\u957f\u5e27\uff081522\uff09\u90a3\u4e48\u5c31\u4f1a\u8f93\u51fa\u201c\u5931\u8d25\u201d\u3010\u8fd9\u4e2a\u4f1a\u4e0d\u4f1a\u592a\u8fc7\u7edd\u5bf9\u4e86\u3011
6.\u6a21\u5757\u590d\u4f4d\u4e4b\u540e\u662f\u8fdb\u5165\u201cRAM\u521d\u59cb\u5316\u201d\u7684\u884c\u4e3a\uff0c\u4f46\u662f\u5b83\u6ca1\u6709\u4e00\u4e2a\u7aef\u53e3\u80fd\u591f\u8bf4\u660e\u201c\u521d\u59cb\u5316\u5b8c\u6210\u201d\u3010\u6b64\u5916\u8fd8\u6709\u4e00\u4e2a\uff1aRAM\u7684a\u53e3\u53ea\u7528\u4e8e\u8d1f\u8d23\u521d\u59cb\u5316\uff0c\u4e4b\u540e\u4e0d\u4f1a\u6709\u4efb\u4f55\u64cd\u4f5c\uff0c\u4e5f\u5c31\u662f\u5229\u7528\u7387\u7684\u95ee\u9898\u3011
7.\u8f6e\u8be2\u53bb\u505a\u201c\u653e\u56de\u201d\u7684\u64cd\u4f5c\uff01\u3010\u9690\u60a3\u3011\uff0c\u201c\u653e\u56de\u201d\u7684\u6570\u91cf\u662fRAM1\u7684\u524d10-bit\u3010\u4e5f\u5c31\u662f\u653e\u56de\u4e00\u4e2a\u56fa\u5b9a\u503c\u3011
*/


`include    "top_define.v"
module  flow_ctrl_top (

                    clk                ,
                    rst_n              ,
                    clk_cpu            ,
                    rst_n_cpu          ,
                    addr               , //\u8fde\u63a5\u5230flow_ctrl_emac
                    addr_en            , //\u8fde\u63a5\u5230flow_ctrl_emac
                    look_fail          , //\u8fde\u63a5\u5230flow_ctrl_emac
                    ram_dp_cfg_register,
                    out_port_num       , //\u8fde\u63a5\u5230flow_ctrl_emac
					frame_length_en    , //\u8fde\u63a5\u5230flow_ctrl_emac
                    frame_length       , //\u8fde\u63a5\u5230flow_ctrl_emac
                    do_not_flow_ctrl   , //\u8fde\u63a5\u5230flow_ctrl_emac

                    cpu_fdata_out      , //\u76f4\u63a5\u8fde\u63a5\u5230RAM1
                    cpu_faddr          , //\u76f4\u63a5\u8fde\u63a5\u5230RAM1
                    cpu_fdata_in       , //\u76f4\u63a5\u8fde\u63a5\u5230RAM1
                    cpu_fread_write    , //\u76f4\u63a5\u8fde\u63a5\u5230RAM1
                    
                    result             , //flow_ctrl_emac\u8f93\u51fa
                                            //\u5b58\u5165receive_schedule\u7684\u4e00\u4e2aFIFO\u4e2d\uff0c\u5e76\u5728\u8bfb\u51fa\u6765\u4e4b\u540e\u7531receive_schedukle\u901a\u77e5fp_class\u6e05\u7a7a \u201cHIMAC\u5e27\u201d\u6216\u8005\u201cEMAC\u5e27\u201d
                                            //\uff08\u6ce8\u610f\uff1a\u5b9a\u4e49\u4e86\u4e24\u79cd\u60c5\u51b5\u6761\u4ef6\uff1a\u67e5\u8868\u5931\u8d25\u548c\u6d41\u63a7\u5931\u8d25\uff0c\u4f46\u662f\u4e0d\u8bba\u662f\u54ea\u79cd\uff0c\u90fd\u4f1a\u6e05\u7a7afp_class\u4e2d\u7684RAM\uff09
                                            //\u95ee\u9898\uff1a\u4f46\u662f\u8fd9\u4e2a\u201c\u6e05\u7a7aRAM\u201d\u64cd\u4f5c\u4f3c\u4e4e\u6709\u70b9\u5947\u602a\uff1a\u5b83\u662f\u5f80FIFO\u4e2d\u5199\u5165\u4e00\u4e2a\u6570
                    result_en          , //flow_ctrl_emac\u8f93\u51fa
                    des_node_id          //flow_ctrl_emac\u8f93\u51fa\uff08\u5916\u90e8\u7a7a\u63a5\uff09
                       );
//**********************
//  DEFINE INPUT//
//**********************
input          clk              ;
input          rst_n            ;
input          clk_cpu          ;
input          rst_n_cpu        ;
input  [1 :0]  out_port_num      ; //2010.12.1 zww
//the following signals come from cam_top module
input  [7 :0]  addr             ;
input          addr_en          ; 
input          look_fail        ;
input	[11:0]	ram_dp_cfg_register; 
input          frame_length_en  ;
input  [10:0]  frame_length     ;//2011.7.26 zww 
input          do_not_flow_ctrl ;
//the following signals come from cpu interface
input  [9 :0]  cpu_faddr        ;
input  [31:0]  cpu_fdata_in     ;
input          cpu_fread_write  ;


//**********************
//DIFINE OUTPUT//
//**********************
output         result           ;
output         result_en        ;
output [7 :0]  des_node_id      ;

output [31:0]  cpu_fdata_out    ;

//**********************
//WIRES//
//**********************
wire   [7 :0]   addr_ram         ;
wire            read_write       ;
wire   [31:0]   token_data_out   ;
wire   [31:0]   token_data_in    ;

wire   [31:0]   q_ram_1          ;
wire   [7 :0]   address_ram_a    ; 
wire            wren_ram_2       ;
wire   [31:0]   data_ram_2       ;
wire   [31:0]   q_ram_2          ; 

// ---------------\ufffd\ufffdinput_token.v\ufffd\ufffdflow_ctrl_emac.v\u05ae\ufffd\ufffd\ufffd\ufffd\ufffd\ufffd\u0368\u0476\ufffd\ufffd\ufffd\u01a3\ufffd\ufffd\ufffd\u05b9\u036c\u02b1\ufffd\ufffdflow_ram_2\ufffd\ufffd\u036c\u04bb\ufffd\ufffd\ufffd\ufffd\u05b7\ufffd\ufffd\ufffd\u0436\ufffd\u0434\ufffd\ufffd\ufffd\ufffd  2011.7.29 ---------------------

wire            busy             ;
wire   [7 :0]   operate_addr     ;

wire flow_ram1_wren;

//*********************************************************
wire ram1_cena, ram2_cena ;

flow_ctrl_emac  u_flow_ctrl_emac   (
                              .clk(clk)                                  ,
                              .rst_n(rst_n)                              ,
                              .addr(addr)                                ,
                              .addr_en(addr_en)                          ,
                              .look_fail(look_fail)                      ,
                              .out_port_num(out_port_num)                ,
							  .frame_length_en(frame_length_en)			 ,
                              .frame_length(frame_length)                , //2011.7.26 zww
                              .do_not_flow_ctrl(do_not_flow_ctrl)        ,
                              .token_data_out(token_data_out)            ,   
                              .result(result)                            ,
                              .result_en(result_en)                      ,
                              .token_data_in(token_data_in)              ,
                              .addr_ram(addr_ram)                        ,
                              .read_write(read_write)                    ,
                              .des_node_id(des_node_id)                  ,
							  .busy(busy)                                ,
							  .operate_addr(operate_addr)
                               );

    reg busy_ff1 ;
    always @( posedge clk or negedge rst_n ) begin
        if( !rst_n )
            busy_ff1 <= 1'b0 ;
        else
            busy_ff1 <= busy ;
    end

`ifdef ASIC
ram_dp_d256_w32_wrapper u_flow_ram_1(
    .clka  ( clk  ),
    .clkb  ( clk_cpu  ),
    .wea   ( flow_ram1_wren   ),
    .web   ( cpu_fread_write   ),
    .addra ( address_ram_a ),
    .addrb ( cpu_faddr[7:0] ),
    .dina  ( data_ram_2  ),
    .dinb  ( cpu_fdata_in  ),
    .douta ( q_ram_1 ),
    .doutb ( cpu_fdata_out ) ,
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .cena(ram1_cena) ,  //
    .cenb(1'b1)         //CPU\u5199\u53e3\uff08\u5fc5\u4f7f\u80fd\uff09
);

ram_dp_d256_w32_wrapper u_flow_ram_2(
    .clka  ( clk  ),
    .clkb  ( clk_cpu  ),
    .wea   ( wren_ram_2   ),
    .web   ( read_write   ),
    .addra ( address_ram_a ),
    .addrb ( addr_ram ),
    .dina  ( data_ram_2  ),
    .dinb  ( token_data_in  ),
    .douta ( q_ram_2 ),
    .doutb ( token_data_out ) ,
    .ram_dp_cfg_register(ram_dp_cfg_register),
    .cena(ram2_cena) ,
    .cenb(busy_ff1) //\u590d\u7528\u4fe1\u53f7
);
`else    
    /*
    RAM1\u683c\u5f0f\uff1a10-bit\u6bcf\u6b21\u589e\u52a0\u4ee4\u724c\u6570 + 22-bir\u6700\u5927\u4ee4\u724c\u6570
    \u7aef\u53e3a\uff1a
        \u5730\u5740\uff1ainput_token\u7ed9\u52308-bit\u5730\u5740
        \u6570\u636e\uff1ainput_token\u7ed9\u523032-bit\u6570\uff08\u548cram\u7684\u6570\u4e00\u6837\uff09
        \u5199\u4f7f\u80fd\uff1ainput_token\u7ed9\u5230
        \u8f93\u51fa\uff1a\u7ed9\u5230input_token\u768432-bit\u6570
    \u7aef\u53e3b\uff1a
        \u5730\u5740\uff1aCPU\u7ed9\u5230\u5730\u5740\u7684\u4f4e8-bit
        \u6570\u636e\uff1aCPU\u7ed9\u5230\u768432-bit\u6570\u636e
        \u5199\u4f7f\u80fd\uff1aCPU\u7ed9\u5230
        \u8f93\u51fa\uff1aCPU\u8bfb\u51fa\u768432-bit\u6570\u636e
    */
flow_ctrl_ram           u_flow_ram_1(
                                .addra(address_ram_a)  ,
                                .addrb(cpu_faddr[7:0]) ,
                                .clka(clk)                  ,
                                .clkb(clk_cpu)              ,
                                .dina(data_ram_2)        ,
                                .dinb(cpu_fdata_in)      ,
                                .wea(flow_ram1_wren)              ,
                                .web(cpu_fread_write)   ,
                                .douta(q_ram_1)     ,
                                .doutb(cpu_fdata_out) ,

                                .ena(ram1_cena) ,  //
                                .enb(1'b1)         //CPU\u5199\u53e3\uff08\u5fc5\u4f7f\u80fd\uff09
                                );
    /*
    RAM2\u683c\u5f0f\uff1a9-bit\u4fdd\u7559 + 1-bit\u542f\u52a8\u6d41\u63a7 + 22-bit\u5f53\u524d\u4ee4\u724c\u6876\u4e2a\u6570
    \u7aef\u53e3a\uff1a
        \u5730\u5740\uff1ainput_token\u7ed9\u52308-bit\u5730\u5740
        \u6570\u636e\uff1ainput_token\u7ed9\u523032-bit\u6570\u636e
        \u5199\u4f7f\u80fd\uff1ainput_token\u7ed9\u5230
        \u8f93\u51fa\uff1a\u7ed9\u5230input_token
    \u7aef\u53e3b\uff1a
        \u5730\u5740\uff1aflow_ctrl_emac\u7ed9\u52308-bit\u5730\u5740
        \u6570\u636e\uff1aflow_ctrl_emac\u7ed9\u523032-bit\u6570\u636e
        \u5199\u4f7f\u80fd\uff1aflow_ctrl_emac\u7ed9\u5230
        \u8f93\u51fa\uff1a\u7ed9\u5230flow_ctrl_emac
    */
flow_ctrl_ram          u_flow_ram_2(
                                .addra(address_ram_a)      ,
                                .addrb(addr_ram)           ,
                                .clka(clk)                  ,
                                .clkb(clk_cpu)              ,
                                .dina(data_ram_2)            ,
                                .dinb(token_data_in)         ,
                                .wea(wren_ram_2)            ,
                                .web(read_write)            ,
                                .douta(q_ram_2)                  ,
                                .doutb(token_data_out) ,

                                .ena(ram2_cena) ,
                                .enb(busy) //\u590d\u7528\u4fe1\u53f7
                                );
`endif

                                
//\u505a\u4e00\u4e2a\u5355\u7eaf\u7684\u201c\u653e\u56de\u64cd\u4f5c\u201d\uff01
input_token       u_input_token(
                                .rst_n(rst_n)                 ,
                                .clk(clk)                     ,
                                .cpu_fread_write(cpu_fread_write) ,
                                .cpu_faddr(cpu_faddr[7:0])    ,
                                .q_a_1(q_ram_1)               ,
                                .q_a_2(q_ram_2)               ,
                                .wren_a_2(wren_ram_2)         ,
                                .data_a_2(data_ram_2)         ,
                                .address_a(address_ram_a)     , //\u540c\u65f6\u8bbf\u95ee\u4e24\u4e2a\u7aef\u53e3\u7684\u5730\u5740
							    .busy(busy)                   ,
							    .operate_addr(operate_addr)   ,
                                .flow_ram1_wren(flow_ram1_wren) ,

                                .ram1_cena(ram1_cena) , //\u8bbf\u95eeram1
                                .ram2_cena(ram2_cena)   //\u8bbf\u95eeram2
                                );
endmodule
 
 
 
 
 
 
 


